Tag Archives: OCP

Peripheral Bus Monitoring

Peripheral Devices
by Matt Richardson

There are 3 very popular standard on-chip buses; in purchase of popular  doption, they are AMBA, OCP, and CoreConnect. Wishbone, an open IP bus nterface, is furthermore discussed for completeness. All these buses employ synonymous inter-onnections and have a range of IP providers supporting bus-compatible cores. There is equally a range of less standard and vendor-proprietary buses that continue o be employed.

AMBA (advanced microcontroller bus architecture) is a family of bus archi-ectures (which come in many types – AHB, APB, AXI) that is managed by but not certified as such) ARM Holdings PLC. The AMBA high-speed bus AHB) is arguably the many popular on-chip bus protocol, with multimaster rbitration, multilayer help, pipelining help, bursting help, and so forth. APB is a easier static bus architecture for peripheral systems. AXI (AMBA xtended interface), the latest AMBA variant, enables numerous great ransactions.

OCP (open-core protocol) is a bus architecture that is managed by the OCP-IP (global partnership). OCP defines a range of complex multicore and multi-channel interfaces that address pipelining, several great purchases, threads and tags, bursting help, etc. OCP is based on a concept of socket-based interfaces that decouple the IP interfaces within the bus cloth to a big extent, permitting a big set of optional OCP interfaces in addition to a
small configurable set of needed data. OCP additionally enables incorporation of user-defined interface signals to address application-specific needs. The OCP debug data discussed later are 1 illustration of the lately defined set of side band data (which can be included into future decades of the OCP standard).

CoreConnect was developed by IBM and is many commonly enjoyed in systems based on IBM PowerPC cores.

It is moreover utilized by Xilinx as an internal bus architecture (in piece because some high-end Xilinx components have integrated PowerPC cores). CoreConnect defines a set of different buses – processor neighborhood bus (PLB), on-chip peripheral (OPB), and device control register (DCR) bus – for different applications. Each bus component of the CoreConnect architec-
ture is optimized to achieve particular on-chip bus architecture objectives.

The PLB delivers a high- bandwidth, low-latency connection between bus agents that are the principal manufacturers and customers of the bus transaction traffic. The OPB delivers a flexible connection path to peripherals and memory of numerous bus widths and transaction timing specifications while providing minimal perfor-system initialization and configuration, and associated control connected transaction traffic within the leading program buses. The DMA controller as well as the interrupt controller cores employ the DCR bus to access general practical registers employed during procedure.

Wishbone is an open-community on-chip bus architecture. It is largely enjoyed in combination with freeware IP blocks. I am not aware of any silicon shape that utilizes it, but it does come up in the literature and is common with all the IP freeware community.

Socket-based interconnect is a standards-oriented approach that concentrates on adding value to the interface socket involving the IP block as well as the bus cloth. Socket-based interconnect is an underlying principle in countless OCP-based architectures, but it could equally be used to alternative bus architectures. Because several bus architectures let addition and selection of numerous bus choices that increase the functionality of the bus interconnect, utilizing a socket-based interface simplifies addition, reduction, or accommodation of the bus interface to the IP blocks, plus the development of test suites to address verification and promoting of the shape.